Contents

• 1. Introduction
  • 1.1. Publications
  • 1.2. Citation
  • 1.3. Indices and tables
• 2. Getting Started
  • 2.1. Join the Corundum community
  • 2.2. Obtaining the source code
  • 2.3. Setting up the FPGA development environment
  • 2.4. Running tests
  • 2.5. Setting up the FPGA build environment (Vivado)
  • 2.6. Building the FPGA configuration
  • 2.7. Building the driver
  • 2.8. Building the userspace tools
  • 2.9. Setting up the PetaLinux build environment
  • 2.10. Loading the FPGA design
  • 2.11. Loading the kernel module
  • 2.12. Testing the design
• 3. Debugging
  • 3.1. The server rebooted when configuring the FPGA
  • 3.2. The link is down
  • 3.3. Ping and iperf don’t work
  • 3.4. The device loses its IP address
• 4. Performance Tuning
• 5. Porting
  • 5.1. Preparation
  • 5.2. Porting Corundum
    • 5.2.1. Board ID
    • 5.2.2. FPGA ID
    • 5.2.3. PCIe interface
    • 5.2.4. Ethernet interfaces
    • 5.2.5. I2C interfaces
    • 5.2.6. Flash access
    • 5.2.7. Module control pins
• 6. Persistent MAC Addresses
  • 6.1. Programming I2C EEPROM via kernel module
• 7. Operations
  • 7.1. Packet transmission
  • 7.2. Packet reception
• 8. Modules
  • 8.1. Overview
    • 8.1.1. High-level overview
  • 8.2. cpl_queue_manager
  • 8.3. cpl_write
  • 8.4. desc_fetch
  • 8.5. mqnic_app_block
    • 8.5.1. Parameters
    • 8.5.2. Ports
  • 8.6. mqnic_core
    • 8.6.1. Parameters
    • 8.6.2. Ports
  • 8.7. mqnic_core_axi
    • 8.7.1. Parameters
    • 8.7.2. Ports
  • 8.8. mqnic_core_pcie
    • 8.8.1. Parameters
    • 8.8.2. Ports
  • 8.9. mqnic_core_pcie_s10
    • 8.9.1. Parameters
    • 8.9.2. Ports
  • 8.10. mqnic_core_pcie_us
    • 8.10.1. Parameters
    • 8.10.2. Ports
  • 8.11. mqnic_egress
  • 8.12. mqnic_ingress
  • 8.13. mqnic_interface
  • 8.14. mqnic_interface_rx
  • 8.15. mqnic_interface_tx
  • 8.16. mqnic_l2_egress
    • 8.16.1. Parameters
    • 8.16.2. Ports
  • 8.17. mqnic_l2_ingress
    • 8.17.1. Parameters
    • 8.17.2. Ports
  • 8.18. mqnic_ptp
    • 8.18.1. Parameters
    • 8.18.2. Ports
  • 8.19. mqnic_ptp_clock
    • 8.19.1. Parameters
    • 8.19.2. Ports
  • 8.20. mqnic_ptp_perout
    • 8.20.1. Parameters
    • 8.20.2. Ports
  • 8.21. mqnic_tx_scheduler_block
    • 8.21.1. Parameters
    • 8.21.2. Ports
  • 8.22. queue_manager
    • 8.22.1. Operation
  • 8.23. rx_checksum
  • 8.24. rx_engine
  • 8.25. rx_hash
  • 8.26. tx_checksum
  • 8.27. tx_engine
  • 8.28. tx_scheduler_rr
    • 8.28.1. Operation
    • 8.28.2. Parameters
    • 8.28.3. Ports
• 9. Register blocks
  • 9.1. App info register block
  • 9.2. Alveo BMC register block
  • 9.3. Gecko BMC register block
  • 9.4. Clock info register block
  • 9.5. Event queue manager register block
    • 9.5.1. Event queue manager CSRs
  • 9.6. Receive completion queue manager register block
    • 9.6.1. Completion queue manager CSRs
  • 9.7. Transmit completion queue manager register block
    • 9.7.1. Completion queue manager CSRs
  • 9.8. DRP register block
  • 9.9. BPI flash register block
  • 9.10. SPI flash register block
  • 9.11. Firmware ID register block
  • 9.12. GPIO register block
  • 9.13. I2C register block
  • 9.14. Interface register block
  • 9.15. Interface control register block
  • 9.16. Null register block
  • 9.17. PTP hardware clock register block
  • 9.18. PTP period output register block
  • 9.19. Port register block
  • 9.20. Port control register block
  • 9.21. Receive queue manager register block
    • 9.21.1. Queue manager CSRs
  • 9.22. Transmit queue manager register block
    • 9.22.1. Queue manager CSRs
  • 9.23. RX queue map register block
  • 9.24. Scheduler block register block
  • 9.25. TDMA scheduler controller register block
    • 9.25.1. TDMA scheduler controller CSRs
  • 9.26. Round-robin scheduler register block
    • 9.26.1. Round-robin scheduler CSRs
  • 9.27. TDMA scheduler register block
    • 9.27.1. TDMA timing parameters
• 10. Device list
  • 10.1. PCIe
  • 10.2. SoC
• 11. Glossary