8.19. mqnic_ptp_clock

mqnic_ptp_clock implements the PTP hardware clock. It wraps ptp_clock and provides a register interface for control, see PTP hardware clock register block.

8.19.1. Parameters

PTP_PERIOD_NS_WIDTH

PTP period ns field width, default 4.

PTP_OFFSET_NS_WIDTH

PTP offset ns field width, default 32.

PTP_FNS_WIDTH

PTP fractional ns field width, default 32.

PTP_PERIOD_NS

PTP nominal period, ns portion 4'd4.

PTP_PERIOD_FNS

PTP nominal period, fractional ns portion 32'd0.

PTP_PEROUT_ENABLE

Enable PTP period output module, default 0.

PTP_PEROUT_COUNT

Number of PTP period output channels, default 1.

REG_ADDR_WIDTH

Register interface address width, default 7.

REG_DATA_WIDTH

Register interface data width, default 32.

REG_STRB_WIDTH

Register interface byte enable width, must be set to (REG_DATA_WIDTH/8).

RB_BASE_ADDR

Base address of control register block, default 0.

RB_NEXT_PTR

Address of next control register block, default 0.

8.19.2. Ports

clk

Logic clock.

Signal	Dir	Width	Description
clk	in	1	Logic clock

rst

Logic reset, active high

Signal	Dir	Width	Description
rst	in	1	Logic reset, active high

reg

Control register interface

Signal	Dir	Width	Description
reg_wr_addr	in	REG_ADDR_WIDTH	Write address
reg_wr_data	in	REG_DATA_WIDTH	Write data
reg_wr_strb	in	REG_STRB_WIDTH	Write byte enable
reg_wr_en	in	1	Write enable
reg_wr_wait	out	1	Write wait
reg_wr_ack	out	1	Write acknowledge
reg_rd_addr	in	REG_ADDR_WIDTH	Read address
reg_rd_en	in	1	Read enable
reg_rd_data	out	REG_DATA_WIDTH	Read data
reg_rd_wait	out	1	Read wait
reg_rd_ack	out	1	Read acknowledge

ptp

PTP signals

Signal	Dir	Width	Description
ptp_pps	out	1	Pulse-per-second
ptp_ts_96	out	96	PTP timestamp
ptp_ts_step	out	1	PTP timestamp step