8.6. mqnic_core
mqnic_core
is the core integration-level module for mqnic for all host interfaces. Contains the interfaces, asynchronous FIFOs, PTP subsystem, statistics collection subsystem, and application block.
For maximum flexibility, this module does not contain the actual host-facing DMA engine, so a wrapper is required to provide the DMA engine with the proper host-facing interface. The available wrappers are:
mqnic_core_pcie for PCI express
mqnic_core_axi for AXI
mqnic_core
integrates the following modules:
stats_counter
: statistics aggregationmqnic_ptp: PTP subsystem
mqnic_interface: NIC interface
mqnic_app_block: Application block
8.6.1. Parameters
- FPGA_ID
FPGA JTAG ID, default is
32'hDEADBEEF
. Reported in Firmware ID register block.
- FW_ID
Firmware ID, default is
32'h00000000
. Reported in Firmware ID register block.
- FW_VER
Firmware version, default is
32'h00_00_01_00
. Reported in Firmware ID register block.
- BOARD_ID
Board ID, default is
16'h1234_0000
. Reported in Firmware ID register block.
- BOARD_VER
Board version, default is
32'h01_00_00_00
. Reported in Firmware ID register block.
- BUILD_DATE
Build date as a 32-bit unsigned Unix timestamp, default is
32'd602976000
. Reported in Firmware ID register block.
- GIT_HASH
32 bits of the git commit hash, default is
32'hdce357bf
. Reported in Firmware ID register block.
- RELEASE_INFO
Additional release info, default is
32'h00000000
. Reported in Firmware ID register block.
- IF_COUNT
Interface count, default
1
.
- PORTS_PER_IF
Ports per interface, default
1
.
- SCHED_PER_IF
Schedulers per interface, default
PORTS_PER_IF
.
- PORT_COUNT
Total port count, must be set to
IF_COUNT*PORTS_PER_IF
.
- CLK_PERIOD_NS_NUM
Numerator of core clock period in ns, default
4
.
- CLK_PERIOD_NS_DENOM
Denominator of core clock period in ns, default
1
.
- PTP_CLK_PERIOD_NS_NUM
Numerator of PTP clock period in ns, default
4
.
- PTP_CLK_PERIOD_NS_DENOM
Denominator of PTP clock period in ns, default
1
.
- PTP_TS_WIDTH
PTP timestamp width, must be
96
.
- PTP_CLOCK_PIPELINE
Output pipeline stages on PTP clock module, default
0
.
- PTP_CLOCK_CDC_PIPELINE
Output pipeline stages on PTP clock CDC module, default
0
.
- PTP_USE_SAMPLE_CLOCK
Use external PTP sample clock, used to synchronize the PTP clock across clock domains, default
0
.
- PTP_SEPARATE_RX_CLOCK
Use
rx_ptp_clk
instead ofrx_clk
for providing current PTP time if set, default0
.
- PTP_PORT_CDC_PIPELINE
Output pipeline stages on PTP clock CDC module, default
0
.
- PTP_PEROUT_ENABLE
Enable PTP period output module, default
0
.
- PTP_PEROUT_COUNT
Number of PTP period output channels, default
1
.
- EVENT_QUEUE_OP_TABLE_SIZE
Event queue manager operation table size, default
32
.
- TX_QUEUE_OP_TABLE_SIZE
Transmit queue manager operation table size, default
32
.
- RX_QUEUE_OP_TABLE_SIZE
Receive queue manager operation table size, default
32
.
- TX_CPL_QUEUE_OP_TABLE_SIZE
Transmit completion queue operation table size, default
TX_QUEUE_OP_TABLE_SIZE
.
- RX_CPL_QUEUE_OP_TABLE_SIZE
Receive completion queue operation table size, default
RX_QUEUE_OP_TABLE_SIZE
.
- EVENT_QUEUE_INDEX_WIDTH
Event queue index width, default
5
. Sets the number of event queues on each interfaces as2**EVENT_QUEUE_INDEX_WIDTH
.
- TX_QUEUE_INDEX_WIDTH
Transmit queue index width, default
13
. Sets the number of transmit queues on each interfaces as2**TX_QUEUE_INDEX_WIDTH
.
- RX_QUEUE_INDEX_WIDTH
Receive queue index width, default
8
. Sets the number of receive queues on each interfaces as2**RX_QUEUE_INDEX_WIDTH
.
- TX_CPL_QUEUE_INDEX_WIDTH
Transmit completion queue index width, default
TX_QUEUE_INDEX_WIDTH
. Sets the number of transmit completion queues on each interfaces as2**TX_CPL_QUEUE_INDEX_WIDTH
.
- RX_CPL_QUEUE_INDEX_WIDTH
Receive completion queue index width, default
RX_QUEUE_INDEX_WIDTH
. Sets the number of receive completion queues on each interfaces as2**RX_CPL_QUEUE_INDEX_WIDTH
.
- EVENT_QUEUE_PIPELINE
Event queue manager pipeline length, default
3
. Tune for best usage of block RAM cascade registers for specified queue count.
- TX_QUEUE_PIPELINE
Transmit queue manager pipeline stages, default
3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0)
. Tune for best usage of block RAM cascade registers for specified queue count.
- RX_QUEUE_PIPELINE
Receive queue manager pipeline stages, default
3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0)
. Tune for best usage of block RAM cascade registers for specified queue count.
- TX_CPL_QUEUE_PIPELINE
Transmit completion queue manager pipeline stages, default
TX_QUEUE_PIPELINE
. Tune for best usage of block RAM cascade registers for specified queue count.
- RX_CPL_QUEUE_PIPELINE
Receive completion queue manager pipeline stages, default
RX_QUEUE_PIPELINE
. Tune for best usage of block RAM cascade registers for specified queue count.
- TX_DESC_TABLE_SIZE
Transmit engine descriptor table size, default
32
.
- RX_DESC_TABLE_SIZE
Receive engine descriptor table size, default
32
.
- RX_INDIR_TBL_ADDR_WIDTH
Receive indirection table size, default
min(RX_QUEUE_INDEX_WIDTH, 8)
.
- TX_SCHEDULER_OP_TABLE_SIZE
Transmit scheduler operation table size, default
TX_DESC_TABLE_SIZE
.
- TX_SCHEDULER_PIPELINE
Transmit scheduler pipeline stages, default
TX_QUEUE_PIPELINE
. Tune for best usage of block RAM cascade registers for specified queue count.
- TDMA_INDEX_WIDTH
TDMA index width, default
6
. Sets the number of TDMA timeslots as2**TDMA_INDEX_WIDTH
.
- PTP_TS_ENABLE
Enable PTP timestamping, default
1
.
- TX_CPL_ENABLE
Enable transmit completions from MAC, default
1
.
- TX_CPL_FIFO_DEPTH
Depth of transmit completion FIFO, default
32
.
- TX_TAG_WIDTH
Transmit tag signal width, default
$clog2(TX_DESC_TABLE_SIZE)+1
.
- TX_CHECKSUM_ENABLE
Enable TCP/UDP checksum offloading on transmit path, default
1
.
- RX_HASH_ENABLE
Enable Toeplitz flow hashing and receive side scaling for RX traffic, default
1
.
- RX_CHECKSUM_ENABLE
Enable TCP/UDP checksum offloading on receive path, default
1
- TX_FIFO_DEPTH
Transmit FIFO depth in bytes, per output port, per traffic class, default
32768
.
- RX_FIFO_DEPTH
Receive FIFO depth in bytes, per output port, default
32768
.
- MAX_TX_SIZE
Maximum packet size on transmit path, default
9214
.
- MAX_RX_SIZE
Maximum packet size on receive path, default
9214
.
- TX_RAM_SIZE
Transmit scratchpad RAM size per interface, default
32768
.
- RX_RAM_SIZE
Receive scratchpad RAM size per interface, default
32768
.
- DDR_CH
Number of DDR memory interfaces, default
1
.
- DDR_ENABLE
Enable DDR memory interfaces, default
0
.
- DDR_GROUP_SIZE
DDR channel group size, default
1
. All channels in each group share the same address space.
- AXI_DDR_DATA_WIDTH
DDR memory interface AXI data width, default
256
.
- AXI_DDR_ADDR_WIDTH
DDR memory interface AXI address width, default
32
.
- AXI_DDR_STRB_WIDTH
DDR memory interface AXI strobe width, default
(AXI_DDR_DATA_WIDTH/8)
.
- AXI_DDR_ID_WIDTH
DDR memory interface AXI ID width, default
8
.
- AXI_DDR_AWUSER_ENABLE
DDR memory interface AXI AWUSER signal enable, default
0
.
- AXI_DDR_AWUSER_WIDTH
DDR memory interface AXI AWUSER signal width, default
1
.
- AXI_DDR_WUSER_ENABLE
DDR memory interface AXI WUSER signal enable, default
0
.
- AXI_DDR_WUSER_WIDTH
DDR memory interface AXI WUSER signal width, default
1
.
- AXI_DDR_BUSER_ENABLE
DDR memory interface AXI BUSER signal enable, default
0
.
- AXI_DDR_BUSER_WIDTH
DDR memory interface AXI BUSER signal width, default
1
.
- AXI_DDR_ARUSER_ENABLE
DDR memory interface AXI ARUSER signal enable, default
0
.
- AXI_DDR_ARUSER_WIDTH
DDR memory interface AXI ARUSER signal width, default
1
.
- AXI_DDR_RUSER_ENABLE
DDR memory interface AXI RUSER signal enable, default
0
.
- AXI_DDR_RUSER_WIDTH
DDR memory interface AXI RUSER signal width, default
1
.
- AXI_DDR_MAX_BURST_LEN
DDR memory interface max AXI burst length, default
256
.
- AXI_DDR_NARROW_BURST
DDR memory interface AXI narrow burst support, default
0
.
- AXI_DDR_FIXED_BURST
DDR memory interface AXI fixed burst support, default
0
.
- AXI_DDR_WRAP_BURST
DDR memory interface AXI wrap burst support, default
0
.
- HBM_CH
Number of HBM memory interfaces, default
1
.
- HBM_ENABLE
Enable HBM memory interfaces, default
0
.
- HBM_GROUP_SIZE
HBM channel group size, default
1
. All channels in each group share the same address space.
- AXI_HBM_DATA_WIDTH
HBM memory interface AXI data width, default
256
.
- AXI_HBM_AHBM_WIDTH
HBM memory interface AXI address width, default
32
.
- AXI_HBM_STRB_WIDTH
HBM memory interface AXI strobe width, default
(AXI_HBM_DATA_WIDTH/8)
.
- AXI_HBM_ID_WIDTH
HBM memory interface AXI ID width, default
8
.
- AXI_HBM_AWUSER_ENABLE
HBM memory interface AXI AWUSER signal enable, default
0
.
- AXI_HBM_AWUSER_WIDTH
HBM memory interface AXI AWUSER signal width, default
1
.
- AXI_HBM_WUSER_ENABLE
HBM memory interface AXI WUSER signal enable, default
0
.
- AXI_HBM_WUSER_WIDTH
HBM memory interface AXI WUSER signal width, default
1
.
- AXI_HBM_BUSER_ENABLE
HBM memory interface AXI BUSER signal enable, default
0
.
- AXI_HBM_BUSER_WIDTH
HBM memory interface AXI BUSER signal width, default
1
.
- AXI_HBM_ARUSER_ENABLE
HBM memory interface AXI ARUSER signal enable, default
0
.
- AXI_HBM_ARUSER_WIDTH
HBM memory interface AXI ARUSER signal width, default
1
.
- AXI_HBM_RUSER_ENABLE
HBM memory interface AXI RUSER signal enable, default
0
.
- AXI_HBM_RUSER_WIDTH
HBM memory interface AXI RUSER signal width, default
1
.
- AXI_HBM_MAX_BURST_LEN
HBM memory interface max AXI burst length, default
256
.
- AXI_HBM_NARROW_BURST
HBM memory interface AXI narrow burst support, default
0
.
- AXI_HBM_FIXED_BURST
HBM memory interface AXI fixed burst support, default
0
.
- AXI_HBM_WRAP_BURST
HBM memory interface AXI wrap burst support, default
0
.
- APP_ID
Application ID, default
0
.
- APP_ENABLE
Enable application section, default
0
.
- APP_CTRL_ENABLE
Enable application section control connection to core NIC registers, default
1
.
- APP_DMA_ENABLE
Enable application section connection to DMA subsystem, default
1
.
- APP_AXIS_DIRECT_ENABLE
Enable lowest-latency asynchronous streaming connection to application section, default
1
- APP_AXIS_SYNC_ENABLE
Enable low-latency synchronous streaming connection to application section, default
1
- APP_AXIS_IF_ENABLE
Enable interface-level streaming connection to application section, default
1
- APP_STAT_ENABLE
Enable application section connection to statistics collection subsystem, default
1
- APP_GPIO_IN_WIDTH
Application section GPIO input signal width, default
32
- APP_GPIO_OUT_WIDTH
Application section GPIO output signal width, default
32
- DMA_ADDR_WIDTH
DMA interface address signal width, default
64
.
- DMA_IMM_ENABLE
DMA interface immediate enable, default
0
.
- DMA_IMM_WIDTH
DMA interface immediate signal width, default
32
.
- DMA_LEN_WIDTH
DMA interface length signal width, default
16
.
- DMA_TAG_WIDTH
DMA interface tag signal width, default
16
.
- IF_RAM_SEL_WIDTH
Width of interface-level select signal, default
1
.
- RAM_SEL_WIDTH
Width of select signal per segment in DMA RAM interface, default
$clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1
.
- RAM_ADDR_WIDTH
Width of address signal for DMA RAM interface, default
$clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE)
.
- RAM_SEG_COUNT
Number of segments in DMA RAM interface, default
2
. Must be a power of 2, must be at least 2.
- RAM_SEG_DATA_WIDTH
Width of data signal per segment in DMA RAM interface, default
256*2/RAM_SEG_COUNT
.
- RAM_SEG_BE_WIDTH
Width of byte enable signal per segment in DMA RAM interface, must be set to
RAM_SEG_DATA_WIDTH/8
.
- RAM_SEG_ADDR_WIDTH
Width of address signal per segment in DMA RAM interface, default
RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH)
.
- RAM_PIPELINE
Number of output pipeline stages in segmented DMA RAMs, default
2
. Tune for best usage of block RAM cascade registers.
- MSI_COUNT
Number of interrupt channels, default
32
.
- AXIL_CTRL_DATA_WIDTH
AXI lite control data signal width, must be set to
32
.
- AXIL_CTRL_ADDR_WIDTH
AXI lite control address signal width, default
16
.
- AXIL_CTRL_STRB_WIDTH
AXI lite control byte enable signal width, must be set to
AXIL_CTRL_DATA_WIDTH/8
.
- AXIL_IF_CTRL_ADDR_WIDTH
AXI lite interface control address signal width, default
AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT)
- AXIL_CSR_ADDR_WIDTH
AXI lite interface CSR address signal width, default
AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8)
- AXIL_CSR_PASSTHROUGH_ENABLE
Enable NIC control register space passthrough, default
0
.
- RB_NEXT_PTR
Next pointer of last register block in the NIC-level CSR space, default
0
.
- AXIL_APP_CTRL_DATA_WIDTH
AXI lite application control data signal width, default
AXIL_CTRL_DATA_WIDTH
. Can be 32 or 64.
- AXIL_APP_CTRL_ADDR_WIDTH
AXI lite application control address signal width, default
16
.
- AXIL_APP_CTRL_STRB_WIDTH
AXI lite application control byte enable signal width, must be set to
AXIL_APP_CTRL_DATA_WIDTH/8
.
- AXIS_DATA_WIDTH
Streaming interface
tdata
signal width, default512
.
- AXIS_KEEP_WIDTH
Streaming interface
tkeep
signal width, must be set toAXIS_DATA_WIDTH/8
.
- AXIS_SYNC_DATA_WIDTH
Synchronous streaming interface
tdata
signal width, defaultAXIS_DATA_WIDTH
.
- AXIS_IF_DATA_WIDTH
Interface streaming interface
tdata
signal width, defaultAXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF)
.
- AXIS_TX_USER_WIDTH
Transmit streaming interface
tuser
signal width, defaultTX_TAG_WIDTH + 1
.
- AXIS_RX_USER_WIDTH
Receive streaming interface
tuser
signal width, default(PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
.
- AXIS_RX_USE_READY
Use
tready
signal on RX interfaces, default0
. If set, logic will exert backpressure withtready
instead of dropping packets when RX FIFOs are full.
- AXIS_TX_PIPELINE
Number of stages in transmit path pipeline FIFO, default
0
. Useful for SLR crossings.
- AXIS_TX_FIFO_PIPELINE
Number of output pipeline stages in transmit FIFO, default
2
. Tune for best usage of block RAM cascade registers.
- AXIS_TX_TS_PIPELINE
Number of stages in transmit path PTP timestamp pipeline FIFO, default
0
. Useful for SLR crossings.
- AXIS_RX_PIPELINE
Number of stages in receive path pipeline FIFO, default
0
. Useful for SLR crossings.
- AXIS_RX_FIFO_PIPELINE
Number of output pipeline stages in receive FIFO, default
2
. Tune for best usage of block RAM cascade registers.
- STAT_ENABLE
Enable statistics collection subsystem, default
1
.
- STAT_INC_WIDTH
Statistics increment signal width, default
24
.
- STAT_ID_WIDTH
Statistics ID signal width, default
12
. Sets the number of statistics counters as2**STAT_ID_WIDTH
.
8.6.2. Ports
- clk
Logic clock. Most interfaces are synchronous to this clock.
Signal
Dir
Width
Description
clk
in
1
Logic clock
- rst
Logic reset, active high
Signal
Dir
Width
Description
rst
in
1
Logic reset, active high
- s_axil_ctrl
AXI-Lite slave interface (control). This interface provides access to the main NIC control register space.
Signal
Dir
Width
Description
s_axil_ctrl_awaddr
in
AXIL_CTRL_ADDR_WIDTH
Write address
s_axil_ctrl_awprot
in
3
Write protect
s_axil_ctrl_awvalid
in
1
Write address valid
s_axil_ctrl_awready
out
1
Write address ready
s_axil_ctrl_wdata
in
AXIL_CTRL_DATA_WIDTH
Write data
s_axil_ctrl_wstrb
in
AXIL_CTRL_STRB_WIDTH
Write data strobe
s_axil_ctrl_wvalid
in
1
Write data valid
s_axil_ctrl_wready
out
1
Write data ready
s_axil_ctrl_bresp
out
2
Write response status
s_axil_ctrl_bvalid
out
1
Write response valid
s_axil_ctrl_bready
in
1
Write response ready
s_axil_ctrl_araddr
in
AXIL_CTRL_ADDR_WIDTH
Read address
s_axil_ctrl_arprot
in
3
Read protect
s_axil_ctrl_arvalid
in
1
Read address valid
s_axil_ctrl_arready
out
1
Read address ready
s_axil_ctrl_rdata
out
AXIL_CTRL_DATA_WIDTH
Read response data
s_axil_ctrl_rresp
out
2
Read response status
s_axil_ctrl_rvalid
out
1
Read response valid
s_axil_ctrl_rready
in
1
Read response ready
- s_axil_app_ctrl
AXI-Lite slave interface (application control). This interface is directly passed through to the application section.
Signal
Dir
Width
Description
s_axil_app_ctrl_awaddr
in
AXIL_APP_CTRL_ADDR_WIDTH
Write address
s_axil_app_ctrl_awprot
in
3
Write protect
s_axil_app_ctrl_awvalid
in
1
Write address valid
s_axil_app_ctrl_awready
out
1
Write address ready
s_axil_app_ctrl_wdata
in
AXIL_APP_CTRL_DATA_WIDTH
Write data
s_axil_app_ctrl_wstrb
in
AXIL_APP_CTRL_STRB_WIDTH
Write data strobe
s_axil_app_ctrl_wvalid
in
1
Write data valid
s_axil_app_ctrl_wready
out
1
Write data ready
s_axil_app_ctrl_bresp
out
2
Write response status
s_axil_app_ctrl_bvalid
out
1
Write response valid
s_axil_app_ctrl_bready
in
1
Write response ready
s_axil_app_ctrl_araddr
in
AXIL_APP_CTRL_ADDR_WIDTH
Read address
s_axil_app_ctrl_arprot
in
3
Read protect
s_axil_app_ctrl_arvalid
in
1
Read address valid
s_axil_app_ctrl_arready
out
1
Read address ready
s_axil_app_ctrl_rdata
out
AXIL_APP_CTRL_DATA_WIDTH
Read response data
s_axil_app_ctrl_rresp
out
2
Read response status
s_axil_app_ctrl_rvalid
out
1
Read response valid
s_axil_app_ctrl_rready
in
1
Read response ready
- m_axil_csr
AXI-Lite master interface (passthrough for NIC control and status). This interface can be used to implement additional components in the main NIC control register space.
Signal
Dir
Width
Description
m_axil_csr_awaddr
in
AXIL_CSR_ADDR_WIDTH
Write address
m_axil_csr_awprot
in
3
Write protect
m_axil_csr_awvalid
in
1
Write address valid
m_axil_csr_awready
out
1
Write address ready
m_axil_csr_wdata
in
AXIL_CTRL_DATA_WIDTH
Write data
m_axil_csr_wstrb
in
AXIL_CTRL_STRB_WIDTH
Write data strobe
m_axil_csr_wvalid
in
1
Write data valid
m_axil_csr_wready
out
1
Write data ready
m_axil_csr_bresp
out
2
Write response status
m_axil_csr_bvalid
out
1
Write response valid
m_axil_csr_bready
in
1
Write response ready
m_axil_csr_araddr
in
AXIL_CTRL_ADDR_WIDTH
Read address
m_axil_csr_arprot
in
3
Read protect
m_axil_csr_arvalid
in
1
Read address valid
m_axil_csr_arready
out
1
Read address ready
m_axil_csr_rdata
out
AXIL_CTRL_DATA_WIDTH
Read response data
m_axil_csr_rresp
out
2
Read response status
m_axil_csr_rvalid
out
1
Read response valid
m_axil_csr_rready
in
1
Read response ready
- ctrl_reg
Control register interface. This interface can be used to implement additional control registers and register blocks in the main NIC control register space.
Signal
Dir
Width
Description
ctrl_reg_wr_addr
out
AXIL_CSR_ADDR_WIDTH
Write address
ctrl_reg_wr_data
out
AXIL_CTRL_DATA_WIDTH
Write data
ctrl_reg_wr_strb
out
AXIL_CTRL_STRB_WIDTH
Write strobe
ctrl_reg_wr_en
out
1
Write enable
ctrl_reg_wr_wait
in
1
Write wait
ctrl_reg_wr_ack
in
1
Write acknowledge
ctrl_reg_rd_addr
out
AXIL_CSR_ADDR_WIDTH
Read address
ctrl_reg_rd_en
out
1
Read enable
ctrl_reg_rd_data
in
AXIL_CTRL_DATA_WIDTH
Read data
ctrl_reg_rd_wait
in
1
Read wait
ctrl_reg_rd_ack
in
1
Read acknowledge
- m_axis_dma_read_desc
DMA read descriptor output
Signal
Dir
Width
Description
m_axis_dma_read_desc_dma_addr
out
DMA_ADDR_WIDTH
DMA address
m_axis_dma_read_desc_ram_sel
out
RAM_SEL_WIDTH
RAM select
m_axis_dma_read_desc_ram_addr
out
RAM_ADDR_WIDTH
RAM address
m_axis_dma_read_desc_len
out
DMA_LEN_WIDTH
Transfer length
m_axis_dma_read_desc_tag
out
DMA_TAG_WIDTH
Transfer tag
m_axis_dma_read_desc_valid
out
1
Request valid
m_axis_dma_read_desc_ready
in
1
Request ready
- s_axis_dma_read_desc_status
DMA read descriptor status input
Signal
Dir
Width
Description
s_axis_dma_read_desc_status_tag
in
DMA_TAG_WIDTH
Status tag
s_axis_dma_read_desc_status_error
in
4
Status error code
s_axis_dma_read_desc_status_valid
in
1
Status valid
- m_axis_dma_write_desc
DMA write descriptor output
Signal
Dir
Width
Description
m_axis_dma_write_desc_dma_addr
out
DMA_ADDR_WIDTH
DMA address
m_axis_dma_write_desc_ram_sel
out
RAM_SEL_WIDTH
RAM select
m_axis_dma_write_desc_ram_addr
out
RAM_ADDR_WIDTH
RAM address
m_axis_dma_write_desc_imm
out
DMA_IMM_WIDTH
Immediate
m_axis_dma_write_desc_imm_en
out
1
Immediate enable
m_axis_dma_write_desc_len
out
DMA_LEN_WIDTH
Transfer length
m_axis_dma_write_desc_tag
out
DMA_TAG_WIDTH
Transfer tag
m_axis_dma_write_desc_valid
out
1
Request valid
m_axis_dma_write_desc_ready
in
1
Request ready
- s_axis_dma_write_desc_status
DMA write descriptor status input
Signal
Dir
Width
Description
s_axis_dma_write_desc_status_tag
in
DMA_TAG_WIDTH
Status tag
s_axis_dma_write_desc_status_error
in
4
Status error code
s_axis_dma_write_desc_status_valid
in
1
Status valid
- dma_ram
DMA RAM interface
Signal
Dir
Width
Description
dma_ram_wr_cmd_sel
in
RAM_SEG_COUNT*RAM_SEL_WIDTH
Write command select
dma_ram_wr_cmd_be
in
RAM_SEG_COUNT*RAM_SEG_BE_WIDTH
Write command byte enable
dma_ram_wr_cmd_addr
in
RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH
Write command address
dma_ram_wr_cmd_data
in
RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH
Write command data
dma_ram_wr_cmd_valid
in
RAM_SEG_COUNT
Write command valid
dma_ram_wr_cmd_ready
out
RAM_SEG_COUNT
Write command ready
dma_ram_wr_done
out
RAM_SEG_COUNT
Write done
dma_ram_rd_cmd_sel
in
RAM_SEG_COUNT*RAM_SEL_WIDTH
Read command select
dma_ram_rd_cmd_addr
in
RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH
Read command address
dma_ram_rd_cmd_valid
in
RAM_SEG_COUNT
Read command valid
dma_ram_rd_cmd_ready
out
RAM_SEG_COUNT
Read command ready
dma_ram_rd_resp_data
out
RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH
Read response data
dma_ram_rd_resp_valid
out
RAM_SEG_COUNT
Read response valid
dma_ram_rd_resp_ready
in
RAM_SEG_COUNT
Read response ready
- msi_irq
MSI request outputs
Signal
Dir
Width
Description
msi_irq
out
MSI_COUNT
Interrupt request
- ptp
PTP clock connections.
Signal
Dir
Width
Description
ptp_clk
in
1
PTP clock
ptp_rst
in
1
PTP reset
ptp_sample_clk
in
1
PTP sample clock
ptp_pps
out
1
PTP pulse-per-second (synchronous to ptp_clk)
ptp_pps_str
out
1
PTP pulse-per-second (stretched) (synchronous to ptp_clk)
ptp_ts_96
out
PTP_TS_WIDTH
current PTP time (synchronous to ptp_clk)
ptp_ts_step
out
1
PTP clock step (synchronous to ptp_clk)
ptp_sync_pps
out
1
PTP pulse-per-second (synchronous to clk)
ptp_sync_ts_96
out
PTP_TS_WIDTH
current PTP time (synchronous to clk)
ptp_sync_ts_step
out
1
PTP clock step (synchronous to clk)
ptp_perout_locked
out
PTP_PEROUT_COUNT
PTP period output locked
ptp_perout_error
out
PTP_PEROUT_COUNT
PTP period output error
ptp_perout_pulse
out
PTP_PEROUT_COUNT
PTP period output pulse
- tx_clk
Transmit clocks, one per port
Signal
Dir
Width
Description
tx_clk
in
PORT_COUNT
Transmit clock
- tx_rst
Transmit resets, one per port
Signal
Dir
Width
Description
tx_rst
in
PORT_COUNT
Transmit reset
- tx_ptp_ts
Reference PTP time for transmit timestamping synchronous to each transmit clock, one per port.
Signal
Dir
Width
Description
tx_ptp_ts_96
out
PORT_COUNT*PTP_TS_WIDTH
current PTP time
tx_ptp_ts_step
out
PORT_COUNT
PTP clock step
- m_axis_tx
Streaming transmit data towards network, one AXI stream interface per port.
Signal
Dir
Width
Description
m_axis_tx_tdata
out
PORT_COUNT*AXIS_DATA_WIDTH
Streaming data
m_axis_tx_tkeep
out
PORT_COUNT*AXIS_KEEP_WIDTH
Byte enable
m_axis_tx_tvalid
out
PORT_COUNT
Data valid
m_axis_tx_tready
in
PORT_COUNT
Ready for data
m_axis_tx_tlast
out
PORT_COUNT
End of frame
m_axis_tx_tuser
out
PORT_COUNT*AXIS_TX_USER_WIDTH
Sideband data
s_axis_tx_tuser
bits, per portBit
Name
Width
Description
0
bad_frame
1
Invalid frame
TX_TAG_WIDTH:1
tx_tag
TX_TAG_WIDTH
Transmit tag
- s_axis_tx_cpl
Transmit completion, one AXI stream interface per port.
Signal
Dir
Width
Description
s_axis_tx_cpl_ts
in
PORT_COUNT*PTP_TS_WIDTH
PTP timestamp
s_axis_tx_cpl_tag
in
PORT_COUNT*TX_TAG_WIDTH
Transmit tag
s_axis_tx_cpl_valid
in
PORT_COUNT
Transmit completion valid
s_axis_tx_cpl_ready
out
PORT_COUNT
Transmit completion ready
- tx_status
Transmit link status inputs, one per port
Signal
Dir
Width
Description
tx_status
in
PORT_COUNT
Transmit link status
- rx_clk
Receive clocks, one per port
Signal
Dir
Width
Description
rx_clk
in
PORT_COUNT
Receive clock
- rx_rst
Receive resets, one per port
Signal
Dir
Width
Description
rx_rst
in
PORT_COUNT
Receive reset
- rx_ptp_ts
Reference PTP time for receive timestamping synchronous to each receive clock, one per port. Synchronous to
rx_ptp_clk
ifPTP_SEPARATE_RX_CLOCK
is set.Signal
Dir
Width
Description
rx_ptp_clk
in
PORT_COUNT
clock for PTP time
rx_ptp_rst
in
PORT_COUNT
reset for PTP time
rx_ptp_ts_96
out
PORT_COUNT*PTP_TS_WIDTH
current PTP time
rx_ptp_ts_step
out
PORT_COUNT
PTP clock step
- s_axis_rx
Streaming receive data from network, one AXI stream interface per port.
Signal
Dir
Width
Description
s_axis_rx_tdata
in
PORT_COUNT*AXIS_DATA_WIDTH
Streaming data
s_axis_rx_tkeep
in
PORT_COUNT*AXIS_KEEP_WIDTH
Byte enable
s_axis_rx_tvalid
in
PORT_COUNT
Data valid
s_axis_rx_tready
out
PORT_COUNT
Ready for data
s_axis_rx_tlast
in
PORT_COUNT
End of frame
s_axis_rx_tuser
in
PORT_COUNT*AXIS_TX_USER_WIDTH
Sideband data
s_axis_rx_tuser
bits, per portBit
Name
Width
Description
0
bad_frame
1
Invalid frame
PTP_TS_WIDTH:1
ptp_ts
PTP_TS_WIDTH
PTP timestamp
- rx_status
Receive link status inputs, one per port
Signal
Dir
Width
Description
rx_status
in
PORT_COUNT
Receive link status
- s_axis_stat
Statistics increment input
Signal
Dir
Width
Description
s_axis_stat_tdata
in
STAT_INC_WIDTH
Statistic increment
s_axis_stat_tid
in
STAT_ID_WIDTH
Statistic ID
s_axis_stat_tvalid
in
1
Statistic valid
s_axis_stat_tready
out
1
Statistic ready
- app_gpio
Application section GPIO
Signal
Dir
Width
Description
app_gpio_in
in
APP_GPIO_IN_WIDTH
GPIO inputs
app_gpio_out
out
APP_GPIO_OUT_WIDTH
GPIO outputs
- app_jtag
Application section JTAG scan chain
Signal
Dir
Width
Description
app_jtag_tdi
in
1
JTAG TDI
app_jtag_tdo
out
1
JTAG TDO
app_jtag_tms
in
1
JTAG TMS
app_jtag_tck
in
1
JTAG TCK